Analysis of carrier transport and heating in ultra-small SOI N-MOSFETs

C. Fiegna*, H. Iwai, E. Sangiorgi, B. Ricco

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Device simulation is adopted to investigate the main implications of scaling SOI MOSFETs to gate length well below 0.1.¿m. Effects of the reduction of silicon layer thickness and of the back oxide thickness are discussed. Reduction of the silicon layer thickness is effective in suppressing short channel effects (SCE) by ensuring better gate control of the back interface. Furthermore, the results of Monte Carlo simulations predict, in agreement with recent experiments, a decrease of hot carrier effects. On the other hand, by reducing the silicon layer thickness, an increase of the carrier transit time may be expected.

Original languageEnglish
Title of host publicationESSDERC 1993 - Proceedings of the 23rd European Solid State Device Research Conference
EditorsJ. P. Noblanc, P. Gentil, M. Verdone, J. Borel, A. Nouailhat
PublisherIEEE Computer Society
Pages675-678
Number of pages4
ISBN (Electronic)2863321358
ISBN (Print)9782863321355
StatePublished - 1993
Event23rd European Solid State Device Research Conference, ESSDERC 1993 - Grenoble, France
Duration: 13 Sep 199316 Sep 1993

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Conference

Conference23rd European Solid State Device Research Conference, ESSDERC 1993
CountryFrance
CityGrenoble
Period13/09/9316/09/93

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    Fiegna, C., Iwai, H., Sangiorgi, E., & Ricco, B. (1993). Analysis of carrier transport and heating in ultra-small SOI N-MOSFETs. In J. P. Noblanc, P. Gentil, M. Verdone, J. Borel, & A. Nouailhat (Eds.), ESSDERC 1993 - Proceedings of the 23rd European Solid State Device Research Conference (pp. 675-678). [5435586] (European Solid-State Device Research Conference). IEEE Computer Society.