Analysis of an SOC architecture for MPEG reconfigurable video coding framework

Jer Min Hsiao*, Chun-Jen Tsai

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

11 Scopus citations


Due to the variety of popular video coding standards, many efforts have been put into the design of a single video decoder chip that supports multiple formats. In 2004, ISO/IEC MPEG started a new work item to facilitate multi-format video codec design and to enable more flexible usage of coding tools. The work item has turned into the MPEG Reconfigurable Video Coding (RVC) framework. The key concept of the RVC framework is to allow flexible reconfiguration of coding tools to create different codec solutions on-the-fly. In this paper, flexible SoC architecture is proposed to support the RVC framework. Some analysis has been conducted to show the extra costs required for this platform compared to hard-wired codec architecture. In conclusion, the RVC framework can be mapped to an SoC platform to provide flexibility and scalability for dynamic application environment with reasonable cost in hardware design.

Original languageEnglish
Article number4252746
Pages (from-to)761-764
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 27 Sep 2007
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: 27 May 200730 May 2007

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