Analysis of abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing non-connected balls

Wen Yu Lo, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

An abnormal failure mechanism due to ESD stressing on the Non-Connected (NC) balls of a high-pin-count (>500 balls) BGA packaged IC is presented. Failure analyses including Scanning Electronic Microscopy (SEM) photographs and the measurement of current waveform during ESD zapping had been performed to give clear explanation on this unusual phenomenon. New protection solutions have been proposed to solve this problem in a BGA packaged IC product with an improvement ESD robustness, which can sustain 3-kV HBM and 300-V MM ESD stresses.

Original languageEnglish
Title of host publicationProceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2003
EditorsPhilip Ho, Daniel Chan, Alastair Trigg, John Thong
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages174-178
Number of pages5
ISBN (Electronic)0780377222
DOIs
StatePublished - 1 Jan 2003
Event10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2003 - Singapore, Singapore
Duration: 11 Jul 2003 → …

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume2003-January

Conference

Conference10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2003
CountrySingapore
CitySingapore
Period11/07/03 → …

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    Lo, W. Y., & Ker, M-D. (2003). Analysis of abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing non-connected balls. In P. Ho, D. Chan, A. Trigg, & J. Thong (Eds.), Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2003 (pp. 174-178). [1222760] (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA.2003.1222760