Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory

C. C. Lu, C. C. Cheng, H. P. Chiu, W. L. Lin, T. W. Chen, S. H. Ku, Wen Jer Tsai, T. C. Lu, K. C. Chen, Ta-Hui Wang, Chih Yuan Lu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Feasibility of multi-times verify (MTV) scheme on triple-level cell (TLC) and quad-level cell (QLC) operations of charge-trap storage 3D NAND memories is investigated comprehensively. Results reveal that random telegraph noise (RTN) and program noise are the major factors affecting lower (LB) and upper boundaries (HB) of Vt distribution, respectively. Enlargement of operation window and reduction of ECC usage with MTV scheme to mitigate RTN-induced LB tail are demonstrated on TLC and QLC operations. In addition, the impact of program noise on HB Vt under various process conditions and ISPP steps is studied experimentally and also explained by our Monte Carlo simulator. Finally, program performance and reserved margin with and without MTV scheme applied on TLC and QLC operation are demonstrated.

Original languageEnglish
Title of host publication2018 IEEE International Electron Devices Meeting, IEDM 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2.2.1-2.2.4
ISBN (Electronic)9781728119878
DOIs
StatePublished - 16 Jan 2019
Event64th Annual IEEE International Electron Devices Meeting, IEDM 2018 - San Francisco, United States
Duration: 1 Dec 20185 Dec 2018

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2018-December
ISSN (Print)0163-1918

Conference

Conference64th Annual IEEE International Electron Devices Meeting, IEDM 2018
CountryUnited States
CitySan Francisco
Period1/12/185/12/18

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    Lu, C. C., Cheng, C. C., Chiu, H. P., Lin, W. L., Chen, T. W., Ku, S. H., Tsai, W. J., Lu, T. C., Chen, K. C., Wang, T-H., & Lu, C. Y. (2019). Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory. In 2018 IEEE International Electron Devices Meeting, IEDM 2018 (pp. 2.2.1-2.2.4). [8614548] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2018.8614548