TY - JOUR
T1 - Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model
AU - Gupta, Chetan
AU - Agarwal, Harshit
AU - Lin, Y. K.
AU - Ito, Akira
AU - Hu, Chen-Ming
AU - Chauhan, Yogesh Singh
PY - 2017/4/1
Y1 - 2017/4/1
N2 - In this paper, we present the modeling of zero-threshold voltage (VTH) bulk MOSFET, also called native devices, using enhanced BSIM6 model. Devices under study show abnormally high leakage current in weak inversion, leading to degraded subthreshold slope. The reasons for such abnormal behavior are identified using technology computer-aided design (TCAD) simulations. Since the zero-VTH transistors have quite low doping, the depletion layer from drain may extend upto the source (at some non-zero value of VDS) which leads to punch-through phenomenon. This source-drain leakage current adds with the main channel current, causing the unexpected current characteristics in these devices. TCAD simulations show that, as we increase the channel length (Leff) and channel doping (NSUB), the source-drain leakage due to punch-through decreases. We propose a model to capture the source-drain leakage in these devices. The model incorporates gate, drain, body biases and channel length as well as channel doping dependency too. The proposed model is validated with the measured data of production level device over various conditions of biases and channel lengths.
AB - In this paper, we present the modeling of zero-threshold voltage (VTH) bulk MOSFET, also called native devices, using enhanced BSIM6 model. Devices under study show abnormally high leakage current in weak inversion, leading to degraded subthreshold slope. The reasons for such abnormal behavior are identified using technology computer-aided design (TCAD) simulations. Since the zero-VTH transistors have quite low doping, the depletion layer from drain may extend upto the source (at some non-zero value of VDS) which leads to punch-through phenomenon. This source-drain leakage current adds with the main channel current, causing the unexpected current characteristics in these devices. TCAD simulations show that, as we increase the channel length (Leff) and channel doping (NSUB), the source-drain leakage due to punch-through decreases. We propose a model to capture the source-drain leakage in these devices. The model incorporates gate, drain, body biases and channel length as well as channel doping dependency too. The proposed model is validated with the measured data of production level device over various conditions of biases and channel lengths.
UR - http://www.scopus.com/inward/record.url?scp=85017123339&partnerID=8YFLogxK
U2 - 10.7567/JJAP.56.04CD09
DO - 10.7567/JJAP.56.04CD09
M3 - Article
AN - SCOPUS:85017123339
VL - 56
JO - Japanese Journal of Applied Physics
JF - Japanese Journal of Applied Physics
SN - 0021-4922
IS - 4
M1 - 04CD09
ER -