Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model

Chetan Gupta, Harshit Agarwal, Y. K. Lin, Akira Ito, Chen-Ming Hu, Yogesh Singh Chauhan

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

In this paper, we present the modeling of zero-threshold voltage (VTH) bulk MOSFET, also called native devices, using enhanced BSIM6 model. Devices under study show abnormally high leakage current in weak inversion, leading to degraded subthreshold slope. The reasons for such abnormal behavior are identified using technology computer-aided design (TCAD) simulations. Since the zero-VTH transistors have quite low doping, the depletion layer from drain may extend upto the source (at some non-zero value of VDS) which leads to punch-through phenomenon. This source-drain leakage current adds with the main channel current, causing the unexpected current characteristics in these devices. TCAD simulations show that, as we increase the channel length (Leff) and channel doping (NSUB), the source-drain leakage due to punch-through decreases. We propose a model to capture the source-drain leakage in these devices. The model incorporates gate, drain, body biases and channel length as well as channel doping dependency too. The proposed model is validated with the measured data of production level device over various conditions of biases and channel lengths.

Original languageEnglish
Article number04CD09
JournalJapanese Journal of Applied Physics
Volume56
Issue number4
DOIs
StatePublished - 1 Apr 2017

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