Analysis and modeling of the gate leakage current in advanced nMOSFET devices with severe gate-to-drain dielectric breakdown

E. Miranda*, T. Kawanago, K. Kakushima, J. Suñé, H. Iwai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

The gate leakage current in advanced metal gate/high-K (EOT ≈ 0.6 nm) nMOSFETs with severe gate-to-drain dielectric breakdown is investigated in detail. Even though several models have been proposed in the past to deal with this issue, they are mainly intended to be used in circuit simulation environments. On the contrary, we report in this work an analytic expression for the gate current based on the solution of the generalized diode equation. The model has been tested not only for positive drain and gate voltage conditions but also for negative biases.

Original languageEnglish
Pages (from-to)1909-1912
Number of pages4
JournalMicroelectronics Reliability
Volume52
Issue number9-10
DOIs
StatePublished - Sep 2012

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