Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits

Kai-Chiang Wu*, Diana Marculescu, Ming Chao Lee, Shih Chieh Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

Device aging, which causes significant loss on circuit performance and lifetime, has been a main factor in reliability degradation of nanoscale designs. Aggressive technology scaling trends, such as thinner gate oxide without proportional downscaling of supply voltage, necessitate an aging-aware analysis and optimization flow in the early design stages. Since PMOS sleep transistors in power-gated circuits suffer from static NBTI during active mode and age very rapidly, the aging of power-gated circuits should be explicitly addressed. In this paper, for power-gated circuits, we present a novel methodology for analyzing and mitigating NBTI-induced performance degradation. Aging effects on both logic networks and sleep transistors are jointly considered for accurate analysis. By introducing 25% redundant sleep transistors with reverse body bias applied, the proposed methodology can significantly mitigate the long-term performance degradation and thus extend the circuit lifetime by 3X.

Original languageEnglish
Title of host publicationIEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Pages139-144
Number of pages6
DOIs
StatePublished - 19 Sep 2011
Event17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan
Duration: 1 Aug 20113 Aug 2011

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Conference

Conference17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
CountryJapan
CityFukuoka
Period1/08/113/08/11

Keywords

  • Aging
  • Leakage
  • NBTI
  • Power gating
  • Reverse body bias

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