The high-order Σ-Δ modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal effects such as the finite op-amp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal effects, we explore several multiple-bit schemes, based on our CIQE high-order Σ-Δ architecture, to remove the non-ideal deterioration. Design rules of these multiple-bit schemes are developed and verified by extensive simulations.
|Number of pages||6|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn|
Duration: 28 Jan 1997 → 31 Jan 1997
|Conference||Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC|
|Period||28/01/97 → 31/01/97|