Analysis and design of multiple-bit high-order Σ-Δ modulator

Hao-Chiao Hong*, Bin Hong Lin, Cheng Wen Wu

*Corresponding author for this work

Research output: Contribution to conferencePaper

3 Scopus citations

Abstract

The high-order Σ-Δ modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal effects such as the finite op-amp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal effects, we explore several multiple-bit schemes, based on our CIQE high-order Σ-Δ architecture, to remove the non-ideal deterioration. Design rules of these multiple-bit schemes are developed and verified by extensive simulations.

Original languageEnglish
Pages419-424
Number of pages6
StatePublished - 1 Jan 1997
EventProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn
Duration: 28 Jan 199731 Jan 1997

Conference

ConferenceProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC
CityChiba, Jpn
Period28/01/9731/01/97

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