Analysis and Design of a New Race-Free Four-Phase CMOS Logic

Chung-Yu Wu, Kuo Hsing Cheng, Jinn Shyan Wang

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

In this paper, a new four-phase dynamic logic, called the high-speed precharge-discharge CMOS logic (HS-PDCMOS logic), is proposed and analyzed. Basically the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus, a complex function can be implemented within a single gate and form the pipelined structured as well. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to partly verify the results of circuit analysis and simulation. It is shown that the HS-PDCMOS logic has an operation speed about 2.5 to 3 times higher than the conventional four-phase dynamic logic. Moreover, the new logic has no clock skew, race, and charge redistribution problems. These advantages make the HS-PDCMOS logic very promising in high-speed complex VLSI design.

Original languageEnglish
Pages (from-to)18-25
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume28
Issue number1
DOIs
StatePublished - 1 Jan 1993

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