Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance - Part I: Model Description

Girish Pahwa, Tapas Dutta, Amit Agarwal, Sourabh Khandelwal, Sayeef Salahuddin, Chen-Ming Hu, Yogesh Singh Chauhan

Research output: Contribution to journalArticle

45 Scopus citations

Abstract

We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau-Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.

Original languageEnglish
Article number7588064
Pages (from-to)4981-4985
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume63
Issue number12
DOIs
StatePublished - 1 Dec 2016

Keywords

  • Compact modeling
  • Negative capacitance FET (NCFET)
  • ferroelectric
  • negative capacitance

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