Analog VLSI design of cellular neural networks with annealing ability

Bing J. Sheu*, Sa H. Bang, Wai-Chi  Fang

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

3 Scopus citations

Abstract

Local interconnection and simple synaptic operators are the most attractive features of the CNN for VLSI implementation in high-speed, real-time applications. Several hardware implementations of the CNN have been reported in the literatures. The CMOS VLSI design of a continuous-time shift-invariant CNN with digitally-programmable operators is considered. In addition, the circuits for hardware annealing is included to provide the flexibility of the network in a variety of applications.

Original languageEnglish
Pages387-392
Number of pages6
StatePublished - 1 Dec 1994
EventProceedings of the 3rd IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94) - Rome, Italy
Duration: 18 Dec 199421 Dec 1994

Conference

ConferenceProceedings of the 3rd IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94)
CityRome, Italy
Period18/12/9421/12/94

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