Analog layout synthesis - Recent advances in topological approaches

H. Graeb*, F. Balasa, R. Castro-Lopez, Y. W. Chang, F. V. Fernandez, Po-Hung Lin, M. Strasser

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

32 Scopus citations

Abstract

This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks.

Original languageEnglish
Title of host publicationProceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
Pages274-279
Number of pages6
DOIs
StatePublished - 22 Oct 2009
Event2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 - Nice, France
Duration: 20 Apr 200924 Apr 2009

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Conference

Conference2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
CountryFrance
CityNice
Period20/04/0924/04/09

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