An universal VLSI architecture for bit-parallel computation in GF(2 m)

Chien Ching Lin*, Fuh Ke Chang, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to conferencePaper

5 Scopus citations

Abstract

In this paper, an universal VLSI architecture for bit-parallel computation in GF(2m) is presented. The proposed architecture is based on Montgomery multiplication algorithm, which is suitable for multiple class of GF(2m) with arbitrary field degree m. Due to the highly regular and modular property, our proposed universal architecture can meet VLSI design requirement. After implemented by 0.18um 1P6M process, our universal architecture can work successfully at 125MHz clock rate. For the finite field multiplier, the total gate count is 1.4K for GF(2m) with any irreducible polynomial of field degree m≤8, whereas the inverse operation can be achieved by the control unit with gate count of 0.3K.1

Original languageEnglish
Pages125-128
Number of pages4
StatePublished - 1 Dec 2004
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 6 Dec 20049 Dec 2004

Conference

Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period6/12/049/12/04

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    Lin, C. C., Chang, F. K., Chang, H-C., & Lee, C-Y. (2004). An universal VLSI architecture for bit-parallel computation in GF(2 m). 125-128. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.