An universal BIST methodology for interconnects

Chiyuao Chang*, Chau-Chin Su

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

In this paper, we propose a methodology for the design and implement of an universal interconnect built-in self test module for boundary scan based interconnects. Such a methodology is able to test any interconnects without knowing their connection configuration in advance.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages1615-1618
Number of pages4
ISBN (Print)0780312813
DOIs
StatePublished - 1 Jan 1993
EventProceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA
Duration: 3 May 19936 May 1993

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Conference

ConferenceProceedings of the 1993 IEEE International Symposium on Circuits and Systems
CityChicago, IL, USA
Period3/05/936/05/93

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