An ultra-low voltage hearing aid chip using variable-latency design technique

Kuo Chiang Chang, Shien Chun Luo, Ching Ji Huang, Chih-Wei Liu, Yuan Hua Chu, Shyh-Jye Jou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2543-2546
Number of pages4
ISBN (Print)9781479934324
DOIs
StatePublished - 1 Jan 2014
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: 1 Jun 20145 Jun 2014

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period1/06/145/06/14

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  • Cite this

    Chang, K. C., Luo, S. C., Huang, C. J., Liu, C-W., Chu, Y. H., & Jou, S-J. (2014). An ultra-low voltage hearing aid chip using variable-latency design technique. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 2543-2546). [6865691] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865691