An RDL-First Fan-out Wafer Level Package for Heterogeneous Integration Applications

Yu Min Lin, Sheng Tsai Wu, Wen Wei Shen, Shin Yi Huang, Tzu Ying Kuo, Ang Ying Lin, Tao Chih Chang, Hsiang Hung Chang, Shu Man Lee, Chia Hsin Lee, Jay Su, Xiao Liu, Qi Wu, Kuan-Neng Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Fan-out wafer-level packaging (FOWLP), a new heterogeneous integration technology, is gradually becoming an attractive solution. Compared with conventional 2.5D/3D IC structures, fan-out WLP does not use a costly interposer element and can have a thin, high-density, and low-cost IC paAdd additional source...ckaging. In this study, a novel fan-out WLP with RDL-first method is demonstrated. Finite element method was used to optimize the warpage control of a reconstituted wafer and to identify the material properties and fabrication for the FOWLP. Calculation results were applied in the design of the test vehicle. Reliability testing of each component level was performed with different techniques such as temperature cycling test (TCT), high temperature storage (HTS) and thermal humidity storage test (THST). The demonstration of RDL-first WLP technology without interposer proves that it has excellent potential for heterogeneous integration applications.

Original languageEnglish
Title of host publicationProceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages349-354
Number of pages6
ISBN (Print)9781538649985
DOIs
StatePublished - 7 Aug 2018
Event68th IEEE Electronic Components and Technology Conference, ECTC 2018 - San Diego, United States
Duration: 29 May 20181 Jun 2018

Publication series

NameProceedings - Electronic Components and Technology Conference
Volume2018-May
ISSN (Print)0569-5503

Conference

Conference68th IEEE Electronic Components and Technology Conference, ECTC 2018
CountryUnited States
CitySan Diego
Period29/05/181/06/18

Keywords

  • Fan-out wafer level packaging
  • Finite element method (FEM)
  • FO-WLP
  • Process development
  • Reliability test

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    Lin, Y. M., Wu, S. T., Shen, W. W., Huang, S. Y., Kuo, T. Y., Lin, A. Y., Chang, T. C., Chang, H. H., Lee, S. M., Lee, C. H., Su, J., Liu, X., Wu, Q., & Chen, K-N. (2018). An RDL-First Fan-out Wafer Level Package for Heterogeneous Integration Applications. In Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018 (pp. 349-354). [8429573] (Proceedings - Electronic Components and Technology Conference; Vol. 2018-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ECTC.2018.00060