An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design

Boyu Hu*, Yuan Du, Rulin Huang, Jeffrey Lee, Young Kai Chen, Mau-Chung Chang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

This brief presents a wireline transmitter architecture, enabling multilevel signaling with feedforward equalization (FFE) in voltage-mode. A compact R2R-DAC-based front end is proposed and analyzed in terms of its speed, power consumption, and linearity. A voltage-mode PAM-4 transmitter with 2-tap FFE utilizing the proposed architecture is implemented in the 65-nm CMOS technology. It achieves a data rate of 34 Gb/s and an energy efficiency of 2.7 mW/Gb/s.

Original languageEnglish
Article number8012497
Pages (from-to)3260-3264
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number11
DOIs
StatePublished - 1 Nov 2017

Keywords

  • Feed-forward equalization (FFE)
  • PAM-4
  • R2R-DAC
  • transmitter
  • voltage-mode

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