An output buffer for 3.3-V applications in a 0.13-μm 1/2.5-V CMOS process

Shih Lun Chen, Ming-Dou Ker

Research output: Contribution to journalArticlepeer-review

20 Scopus citations

Abstract

With a 3.3-V interface, such as PCI-X application, high-voltage overstress on the gate oxide is a serious reliability problem in designing I/O circuits by using only 1/2.5-V low-voltage devices in a 0.13-μm CMOS process. Thus, a new output buffer realized with low-voltage (1- and 2.5-V) devices to drive high-voltage signals for 3.3-V applications is proposed in this paper. The proposed output buffer has been fabricated in a 0.13-μm 1/2.5-V 1P8M CMOS process with Cu interconnects. The experimental results have confirmed that the proposed output buffer can be successfully operated at 133 MHz without suffering high-voltage gate-oxide overstress in the 3.3-V interface. In addition, a new level converter that is realized with only 1- and 2.5-V devices that can convert 0/1-V voltage swing to 1/3.3-V voltage swing is also presented in this paper. The experimental results have also confirmed that the proposed level converter can be operated correctly.

Original languageEnglish
Pages (from-to)14-18
Number of pages5
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume54
Issue number1
DOIs
StatePublished - 1 Jan 2007

Keywords

  • Gate-oxide reliability
  • level converter
  • mixed-voltage I/O
  • output buffer

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