An optimal silicidation technique for electrostatic discharge protection sub-100 nm CMOS devices in VLSI circuit

Shao Ming Yu, Jam Wen Lee, Yiming Li*

*Corresponding author for this work

Research output: Contribution to journalArticle

Abstract

In this paper we propose a silicide design consideration for electrostatic discharge (ESD) protection in nanoscale CMOS devices. According to our practical implementation, it is found that a comprehensive silicide optimization can be achieved on the gate, drain, and source sides with very few testkey designs. Our study shows that there is a high characteristic efficiency for various conditions; in particular, for optimizing the performance of sub-100 nm complementary metal-oxide-semiconductor devices in system-on-a-chip era.

Original languageEnglish
Pages (from-to)213-217
Number of pages5
JournalMicroelectronic Engineering
Volume84
Issue number2
DOIs
StatePublished - Feb 2007

Keywords

  • Electrostatic discharge
  • Modeling
  • Nanoscale device
  • Optimization
  • Silicide
  • Simulation
  • System-on-a-chip
  • VLSI circuit

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