An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

James C. Chen*, Dennis Sylvester, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

30 Scopus citations

Abstract

A simple, accurate method of measuring interconnect capacitances is presented. The test structure has excellent resolution, needs only DC measurements, and is compact enough for scribe-line implementation. These qualities make it suitable for measurement-based, interconnect capacitance characterization in a comparable fashion to current characterization efforts for MOSFET devices. The entire characterization scheme is demonstrated for a production 0.5-μm, three-level metal technology. The method not only provides an accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlevel dielectric (ILD) thickness and drawn width reductions for process control as well.

Original languageEnglish
Pages (from-to)204-210
Number of pages7
JournalIEEE Transactions on Semiconductor Manufacturing
Volume11
Issue number2
DOIs
StatePublished - 1 Dec 1998

Keywords

  • Capacitance measurement
  • Integrated circuit interconnections
  • Modeling
  • Monitoring
  • Test structures

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