An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

James C. Chen; Dennis Sylvester; Chen-Ming Hu

doi:10.1109/66.670160

An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

James C. Chen^*, Dennis Sylvester, Chen-Ming Hu

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Contribution to journal › Article › peer-review

30 Scopus citations

Abstract

A simple, accurate method of measuring interconnect capacitances is presented. The test structure has excellent resolution, needs only DC measurements, and is compact enough for scribe-line implementation. These qualities make it suitable for measurement-based, interconnect capacitance characterization in a comparable fashion to current characterization efforts for MOSFET devices. The entire characterization scheme is demonstrated for a production 0.5-μm, three-level metal technology. The method not only provides an accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlevel dielectric (ILD) thickness and drawn width reductions for process control as well.

Original language	English
Pages (from-to)	204-210
Number of pages	7
Journal	IEEE Transactions on Semiconductor Manufacturing
Volume	11
Issue number	2
DOIs	https://doi.org/10.1109/66.670160
State	Published - 1 Dec 1998

Keywords

Capacitance measurement
Integrated circuit interconnections
Modeling
Monitoring
Test structures

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N2 - A simple, accurate method of measuring interconnect capacitances is presented. The test structure has excellent resolution, needs only DC measurements, and is compact enough for scribe-line implementation. These qualities make it suitable for measurement-based, interconnect capacitance characterization in a comparable fashion to current characterization efforts for MOSFET devices. The entire characterization scheme is demonstrated for a production 0.5-μm, three-level metal technology. The method not only provides an accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlevel dielectric (ILD) thickness and drawn width reductions for process control as well.

AB - A simple, accurate method of measuring interconnect capacitances is presented. The test structure has excellent resolution, needs only DC measurements, and is compact enough for scribe-line implementation. These qualities make it suitable for measurement-based, interconnect capacitance characterization in a comparable fashion to current characterization efforts for MOSFET devices. The entire characterization scheme is demonstrated for a production 0.5-μm, three-level metal technology. The method not only provides an accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlevel dielectric (ILD) thickness and drawn width reductions for process control as well.

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KW - Integrated circuit interconnections

KW - Modeling

KW - Monitoring

KW - Test structures

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An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

Abstract

Keywords

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