An offset cancellation technique for two-stage CMOS operational amplifiers

Chih Wen Lu*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

An offset cancellation technique for two-stage CMOS operational amplifiers is proposed. The auxiliary amplifiers are employed to cancel the offset voltage. The error voltage is stored on a capacitor during the cancellation phase and is canceled during the normal operation. An experimental prototype amplifier implemented in a 0.35-μm CMOS technology demonstrates that the offset voltage is reduced to 1.898 mV under a clock frequency of 200 KHz.

Original languageEnglish
Title of host publicationProceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
Pages154-156
Number of pages3
DOIs
StatePublished - 2007
Event2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, TX, United States
Duration: 30 May 20071 Jun 2007

Publication series

NameProceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Conference

Conference2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
CountryUnited States
CityAustin, TX
Period30/05/071/06/07

Keywords

  • Offset
  • Offset cancellation
  • Offset voltage
  • Op-amp
  • Operational amplifier

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