An I/O scheduling strategy for embedded flash storage devices with mapping cache

Cheng Ji, Li-Pin Chang, Chao Wu, Liang Shi*, Chun Jason Xue

*Corresponding author for this work

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

NAND flash memory has been the default storage component in embedded systems. One of the key technologies for flash management is the address mapping scheme between logical addresses and physical addresses, which deals with the inability of in-place-updating in flash memory. Demand-based page-level mapping cache is often applied to match the cache size constraint and performance requirement of embedded storage systems. However, recent studies showed that the management overhead of mapping cache schemes is sensitive to the host I/O patterns, especially when the mapping cache is small. This paper presents a novel I/O scheduling scheme, called MAP+, to alleviate this problem. The proposed scheduling approach reorders I/O requests for performance improvement from two angles. Prioritizing the requests that will hit in the mapping cache, and grouping requests with related logical addresses into large batches. Batches of requests are reordered to further optimize request waiting time. Experimental results show that MAP+ improved upon traditional I/O schedulers by 48% and 18% in terms of read and write latencies, respectively.

Original languageEnglish
Article number7987082
Pages (from-to)756-769
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume37
Issue number4
DOIs
StatePublished - 1 Apr 2018

Keywords

  • Embedded system
  • Flash memory performance
  • I/O scheduling
  • Mapping cache

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