An inverter based 2-MHz 42-μW △Σ ADC with 20-KHz bandwidth and 66dB dynamic range

Chau-Chin Su*, Po Chen Lin, Hung Wen Lu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

10 Scopus citations

Abstract

This paper presented an inverter based 3rdorder sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancel-lation. The ADC has been implemented in TSMC 2P6M 0.18μm CMOS technology with a core area of 0.54mm2 The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42μW and the dynamic range of 66.02dB.

Original languageEnglish
Pages63-66
Number of pages4
DOIs
StatePublished - 1 Dec 2006
Event2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China
Duration: 13 Nov 200615 Nov 2006

Conference

Conference2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
CountryChina
CityHangzhou
Period13/11/0615/11/06

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