This paper presented an inverter based 3rdorder sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancel-lation. The ADC has been implemented in TSMC 2P6M 0.18μm CMOS technology with a core area of 0.54mm2 The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42μW and the dynamic range of 66.02dB.
|Number of pages||4|
|State||Published - 1 Dec 2006|
|Event||2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China|
Duration: 13 Nov 2006 → 15 Nov 2006
|Conference||2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006|
|Period||13/11/06 → 15/11/06|