@inproceedings{d9cc3c3730d24aac92c66f9ecde42bfd,
title = "An inter-frame/inter-view cache architecture design for multi-view video decoders",
abstract = "In this paper we propose a low-bandwidth two-level inter-frame/inter-view cache architecture for a view scalable multi-view video decoder, which adopts two decoder cores to decode multi-view videos in parallel. The first level L1 cache is developed for the single video decoder core, which is able to reduce 60% bandwidth in doing inter-frame prediction in average. Moreover, we develop the second level L2 cache architecture to reuse the same reference data for doing inter-view prediction among different decoder cores, which can further reduce 35% bandwidth. By adopting the proposed two-level cache architecture for doing inter-frame/inter-view prediction, we can reduce 80% bandwidth through a view scalable multi-view video decoder implementation, which achieves real-time HD1080 dual-view video decoding.",
author = "Lee, {Jui Sheng} and Wang, {Sheng Han} and Chou, {Chih Tai} and Chien, {Cheng An} and Chang, {Hsiu Cheng} and Jiun-In Guo",
year = "2012",
month = dec,
day = "1",
language = "English",
isbn = "9780615700502",
series = "2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012",
booktitle = "2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012",
note = "null ; Conference date: 03-12-2012 Through 06-12-2012",
}