An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology

Chia Ling Chang*, Chia Ching Chang, Hui Ling Chan, Charles H.P. Wen, Jayanta Bhadra

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Iddq testing has been a critical integral component in test suites for screening unreliable devices. As the silicon technology keeps shrinking, Iddq values and their variation increase as well. Moreover, along with rapid design scaling, defect-induced leakage currents become less significant when compared to full-chip current and also make themselves less distinguishable. Traditional Iddq methods become less effective and cause more test escapes and yield loss. Therefore, in this paper, a new test method named σ-Iddq testing is proposed and integrates (1) a variation-aware full-chip leakage estimator and (2) a clustering algorithm to classify chip without using threshold values. Experimental result shows that σ-Iddq testing achieves a higher classification accuracy in a 45nm technology when compared to a single-threshold Iddq testing. As a result, both the process-variation and design-scaling impacts are successfully excluded and thus the defective chips can be identified intelligently.

Original languageEnglish
Title of host publicationASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
Pages163-168
Number of pages6
DOIs
StatePublished - 26 Apr 2012
Event17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 - Sydney, NSW, Australia
Duration: 30 Jan 20122 Feb 2012

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
CountryAustralia
CitySydney, NSW
Period30/01/122/02/12

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    Chang, C. L., Chang, C. C., Chan, H. L., Wen, C. H. P., & Bhadra, J. (2012). An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology. In ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference (pp. 163-168). [6164938] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2012.6164938