An integrated placement and routing for ratioed capacitor array based on ILP formulation

Pang Yen Chou, Po-Hung Lin, Helmut Graeb

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Capacitor arrays are widely used in analog and mixed-signal circuit design. Most previous works solve the placement and routing problem either in a two-stage fashion or iteratively in loops, which may be more time-consuming or have less routing consideration in the placement step. To our best knowledge, this work is the first to formulate capacitor array placement and routing problem together and solve at once. Experimental results show that the proposed approach requires shorter time to reach comparable results to previous work. The formulation also provides possibilities for adding more placement and routing constraints in the future if they can fit into the Integer Linear Programming (ILP) form.

Original languageEnglish
Title of host publication2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467394987
DOIs
StatePublished - 31 May 2016
Event2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
Duration: 25 Apr 201627 Apr 2016

Publication series

Name2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Conference

Conference2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
CountryTaiwan
CityHsinchu
Period25/04/1627/04/16

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