An integrated 60-GHz front-end receiver with a frequency tripler using 0.13-um CMOS technology

Po-Hung Chen*, Min Chiao Chen, Chung-Yu Wu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In this paper, a 60-GHz CMOS direct-conversion receiver integrated with a frequency tripler is proposed. The proposed receiver consists of a low-noise amplifier (LNA), a down-conversion mixer, output buffers, and a frequency tripler. This chip is designed using 0.13-um CMOS technology. By using a frequency tripler, the operating frequency of the PLL can be reduced from 60 GHz to 20 GHz. This makes the implementation of the PLL much easier. According to the simulation results, the receiver has a noise figure (NF) of 7.6 dB, a power gain of 29.2 dB. It consumes 14.2 mW from a 1.2-V power supply.

Original languageEnglish
Title of host publicationICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
Pages829-832
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco
Duration: 11 Dec 200714 Dec 2007

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
CountryMorocco
CityMarrakech
Period11/12/0714/12/07

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  • Cite this

    Chen, P-H., Chen, M. C., & Wu, C-Y. (2007). An integrated 60-GHz front-end receiver with a frequency tripler using 0.13-um CMOS technology. In ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems (pp. 829-832). [4511119] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). https://doi.org/10.1109/ICECS.2007.4511119