An incremental learning framework for estimating signal controllability in unit-level verification

Charles H.P. Wen, Li C. Wang, Jayanta Bhadra

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Unit-level verification is a critical step to the success of full-chip functional verification for microprocessor designs. In the unit-level verification, a unit is first embedded in a complex software that emulates the behavior of surrounding units, and then a sequence of stimuli is applied to measure the functional coverage. In order to generate such a sequence, designers need to comprehend the relationship between boundaries at the unit under verification and at the inputs to the emulation software. However, figuring out this relationship can be very difficult. Therefore, this paper1 proposes an incremental learning framework that incorporates an ordered-binary-decision-forest(OBDF) algorithm, to automate estimating the controllability of unit-level signals and to provide full-chip level information for designers to govern these signals. Mathematical analysis shows that the proposed OBDF algorithm has lower model complexity and lower error variance than the previous algorithms. Meanwhile, a commercial microprocessor core is also applied to demonstrate that controllability of input signals on the load/store unit in the microprocessor core can be estimated automatically and information about how to govern these signals can also be extracted successfully.

Original languageEnglish
Title of host publication2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD
Pages250-257
Number of pages8
DOIs
StatePublished - 1 Dec 2007
Event2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD - San Jose, CA, United States
Duration: 4 Nov 20078 Nov 2007

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Conference

Conference2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD
CountryUnited States
CitySan Jose, CA
Period4/11/078/11/07

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    Wen, C. H. P., Wang, L. C., & Bhadra, J. (2007). An incremental learning framework for estimating signal controllability in unit-level verification. In 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD (pp. 250-257). [4397274] (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD). https://doi.org/10.1109/ICCAD.2007.4397274