An improved noc design methodology using latency-guarantee network architecture and communication-contention-aware cost function

Liang Yu Lin, Cheng Yeh Wang, Lan-Da Van

Research output: Contribution to journalArticlepeer-review

Abstract

In this paper, we propose an on-chip latency-guarantee network architecture and communication contention-aware cost function that can be applied to task mapping and communication path assignments for Network-on-Chip (NoC). The proposed switch as an essential component of the network architecture has three main features: (1) bandwidth guarantee; (2) economical memory usage; and (3) deadlock free. The underlying principle which enable the functioning of these three features include exploiting virtual-circuit switching with dedicated connection paths, determined by path assignment algorithm, virtual channel flow control with request-oriented weighted round-robin scheduling and the pipeline bus. In order to utilize this infrastructure and to consider the side effects of the contention in the on-chip communication, the contention-aware cost function was developed to improve task mapping and the communication path assignment algorithm such that the overall system throughput is maximized. Using this approach, the comparison of the task mapping without the consideration of communication with the contention effect, the overall system showed that the throughput improved by 50% under the communication dominated system while the latency improved by 9.8%.

Original languageEnglish
Pages (from-to)179-190
Number of pages12
JournalInternational Journal of Electrical Engineering
Volume19
Issue number4
StatePublished - 1 Aug 2012

Keywords

  • Design automation
  • Design methodology
  • Network architecture
  • Network-onchip (nocs)
  • Optimization.

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