An implementation of performance-driven block and I/O placement for chip-package codesign

Ming Fang Lai*, Hung-Ming Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

As silicon technology scales, we can integrate more and more circuits on a single chip, which means more I/Os are needed in modern designs. The flip-chip technology which was developed by IBM is better suited for I/O increase than the typical peripheral wire-bond design. One of the most important characteristics of flip-chip designs is that the I/O buffers could be placed anywhere inside a chip, just like core cells. Motivated by [14] in proposing various I/O planning constraints, we develop a block and I/O buffer placement method in wirelength and signal skew optimization (especially for differential pair signals), and power integrity awareness for chip-package codesign. The results have shown that our approach takes care of power integrity and outperforms [12] in weighted performance metrics optimization.

Original languageEnglish
Title of host publicationProceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008
Pages604-607
Number of pages4
DOIs
StatePublished - 25 Aug 2008
Event9th International Symposium on Quality Electronic Design, ISQED 2008 - San Jose, CA, United States
Duration: 17 Mar 200819 Mar 2008

Publication series

NameProceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Conference

Conference9th International Symposium on Quality Electronic Design, ISQED 2008
CountryUnited States
CitySan Jose, CA
Period17/03/0819/03/08

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