An implementation of integrable low power techniques for modern cell-based VLSI designs

Ming Chung Lee*, Her-Ming Chiueh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recent research has proposed several low-power design techniques for VLSI circuitry in nano-scale CMOS era. However, these techniques always involve custom layout design or novel EDA flows. In this paper essential low power techniques such as voltage separation, body bias and power switch are implemented in existent place and route (P&R) tools. These techniques enable the possibility to integrated low power techniques into standard Cell-Based physical design flow. The result of these research shows a little overhead in design procedure equally area overhead compare with fully custom design flow. The proposed low power design techniques can be cooperated with modern power management system to enable the power reduction in targeting circuitry with small implementation overheads.

Original languageEnglish
Title of host publicationICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
Pages890-893
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems - Nice, France
Duration: 10 Dec 200613 Dec 2006

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

ConferenceICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
CountryFrance
CityNice
Period10/12/0613/12/06

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  • Cite this

    Lee, M. C., & Chiueh, H-M. (2006). An implementation of integrable low power techniques for modern cell-based VLSI designs. In ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems (pp. 890-893). [4263510] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). https://doi.org/10.1109/ICECS.2006.379932