In this paper, we propose a 4×4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders , which adopt macroblock level pipelines, our proposed 4x4-block level pipelining architecture of H.264/AVC decoder achieves better hardware utilization. Moreover, our proposed decoding ordering can effectively save memory access and reduce processing cycles, which results in 260,000 MB/s under 100MHz clock frequency. By adopting these two techniques, our proposed design supports real time decoding with 1080HD (1920x1088) video sequence in 30fps (244,800 MB/s required) and level 4 of baseline profile.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Dec 2005|
|Event||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
Duration: 23 May 2005 → 26 May 2005