AN H.264/AVC decoder with 4x4-block level pipeline

Ting An Lin; Sheng Zen Wang; Tsu Ming Liu; Chen-Yi Lee

doi:10.1109/ISCAS.2005.1464961

AN H.264/AVC decoder with 4x4-block level pipeline

Ting An Lin^*, Sheng Zen Wang, Tsu Ming Liu, Chen-Yi Lee

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Conference article › peer-review

27 Scopus citations

Abstract

In this paper, we propose a 4×4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders [1][2], which adopt macroblock level pipelines, our proposed 4x4-block level pipelining architecture of H.264/AVC decoder achieves better hardware utilization. Moreover, our proposed decoding ordering can effectively save memory access and reduce processing cycles, which results in 260,000 MB/s under 100MHz clock frequency. By adopting these two techniques, our proposed design supports real time decoding with 1080HD (1920x1088) video sequence in 30fps (244,800 MB/s required) and level 4 of baseline profile.

Original language	English
Article number	1464961
Pages (from-to)	1810-1813
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1464961
State	Published - 1 Dec 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

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title = "AN H.264/AVC decoder with 4x4-block level pipeline",

abstract = "In this paper, we propose a 4×4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders [1][2], which adopt macroblock level pipelines, our proposed 4x4-block level pipelining architecture of H.264/AVC decoder achieves better hardware utilization. Moreover, our proposed decoding ordering can effectively save memory access and reduce processing cycles, which results in 260,000 MB/s under 100MHz clock frequency. By adopting these two techniques, our proposed design supports real time decoding with 1080HD (1920x1088) video sequence in 30fps (244,800 MB/s required) and level 4 of baseline profile.",

author = "Lin, {Ting An} and Wang, {Sheng Zen} and Liu, {Tsu Ming} and Chen-Yi Lee",

year = "2005",

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doi = "10.1109/ISCAS.2005.1464961",

language = "English",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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note = "null ; Conference date: 23-05-2005 Through 26-05-2005",

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T1 - AN H.264/AVC decoder with 4x4-block level pipeline

AU - Lin, Ting An

AU - Wang, Sheng Zen

AU - Liu, Tsu Ming

AU - Lee, Chen-Yi

PY - 2005/12/1

Y1 - 2005/12/1

N2 - In this paper, we propose a 4×4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders [1][2], which adopt macroblock level pipelines, our proposed 4x4-block level pipelining architecture of H.264/AVC decoder achieves better hardware utilization. Moreover, our proposed decoding ordering can effectively save memory access and reduce processing cycles, which results in 260,000 MB/s under 100MHz clock frequency. By adopting these two techniques, our proposed design supports real time decoding with 1080HD (1920x1088) video sequence in 30fps (244,800 MB/s required) and level 4 of baseline profile.

AB - In this paper, we propose a 4×4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders [1][2], which adopt macroblock level pipelines, our proposed 4x4-block level pipelining architecture of H.264/AVC decoder achieves better hardware utilization. Moreover, our proposed decoding ordering can effectively save memory access and reduce processing cycles, which results in 260,000 MB/s under 100MHz clock frequency. By adopting these two techniques, our proposed design supports real time decoding with 1080HD (1920x1088) video sequence in 30fps (244,800 MB/s required) and level 4 of baseline profile.

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