AN H.264/AVC decoder with 4x4-block level pipeline

Ting An Lin*, Sheng Zen Wang, Tsu Ming Liu, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

27 Scopus citations

Abstract

In this paper, we propose a 4×4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders [1][2], which adopt macroblock level pipelines, our proposed 4x4-block level pipelining architecture of H.264/AVC decoder achieves better hardware utilization. Moreover, our proposed decoding ordering can effectively save memory access and reduce processing cycles, which results in 260,000 MB/s under 100MHz clock frequency. By adopting these two techniques, our proposed design supports real time decoding with 1080HD (1920x1088) video sequence in 30fps (244,800 MB/s required) and level 4 of baseline profile.

Original languageEnglish
Article number1464961
Pages (from-to)1810-1813
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 1 Dec 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 23 May 200526 May 2005

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