@inproceedings{1f07950b1fa940b38c555672571b03c3,
title = "An FPGA-based bwt accelerator for bzip2 data compression",
abstract = "The Burrows-Wheeler Transform (BWT) has played an important role in lossless data compression algorithms. To achieve a good compression ratio, the BWT block size needs to be several hundreds of kilobytes, which requires a large amount of on-chip memory resources and limits effective hardware implementations. In this paper, we analyze the bottleneck of the BWT acceleration and present a novel design to map the anti-sequential suffix sorting algorithm to FPGAs. Our design can perform BWT with a block size of up to 500KB (i.e., bzip2 level 5 compression) on the Xilinx Virtex UltraScale+ VCU1525 board, while the state-of-Art FPGA implementation can only support 4KB block size. Experiments show our FPGA design can achieve ~2x speedup compared to the best CPU implementation using standard large Corpus benchmarks.",
keywords = "BWT, Compression, FPGA",
author = "Weikang Qiao and Zhenman Fang and Chang, {Mau Chung Frank} and Jason Cong",
year = "2019",
month = apr,
doi = "10.1109/FCCM.2019.00023",
language = "English",
series = "Proceedings - 27th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "96--99",
booktitle = "Proceedings - 27th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019",
address = "United States",
note = "null ; Conference date: 28-04-2019 Through 01-05-2019",
}