An Experimental 4-Mbit CMOS EEPROM with a nand-Structured Cell

Masaki Momodomi, Y. Yasuoitoh, Shirota Riichiro, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Seiichi Aritome, Tetsuo Endoh, Kazunori Ohuchi, Fujio Masuoka

Research output: Contribution to journalArticlepeer-review

26 Scopus citations

Abstract

A 5-V-only high-density (5I2K × 8 bit) electrically erasable and programmable read-only memory (EEPROM) has been designed and fabricated by using a nand-structured cell with 1.0-μm design rules. The average cell area per bit is 12.9 μm2. Block erasing, successive program-ming, and random reading are achieved using a newly developed NAND-cell control circuit. Typical erasing time is 1.0 ms and page-programming time is 4.0 ms, equivalent to 1.0 s/bit. A dynamic sensing system is introduced to sense the small cell current. Typical read access time is 1.6 ps. The die size is 10,7 × 15.3 mm2.

Original languageEnglish
Pages (from-to)1238-1243
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume24
Issue number5
DOIs
StatePublished - 1 Jan 1989

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