An event-driven incremental timing fault simulator

Shyh-Jye Jou, Wen Zen Shen, Shwu Huey Chiou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An efficient MOS multiple sets of multiple faults simulator with electrical timing information is presented. By using event-driven, selective trace and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior in speedup, extra memory used and precision to other approaches. Moreover, this simulator is suited for parallel simulation in a multiprocessor system.

Original languageEnglish
Title of host publication1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages424-427
Number of pages4
ISBN (Electronic)078030036X, 9780780300361
DOIs
StatePublished - 1 Jan 1991
Event1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991 - Taipei, Taiwan
Duration: 22 May 199124 May 1991

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)1930-8868

Conference

Conference1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991
CountryTaiwan
CityTaipei
Period22/05/9124/05/91

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    Jou, S-J., Shen, W. Z., & Chiou, S. H. (1991). An event-driven incremental timing fault simulator. In 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991 (pp. 424-427). [246754] (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VTSA.1991.246754