An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions

Wei Hung Du; Ming Hung Chang; Hao Yi Yang; Wei Hwang

doi:10.1109/SOCC.2011.6085069

An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions

Wei Hung Du^*, Ming Hung Chang, Hao Yi Yang, Wei Hwang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

In this paper, an ultra-low power (ULP) 16Kb SRAM-based first-in first-out (FIFO) memory is proposed for wireless body area networks (WBANs). The proposed FIFO memory is capable of operating in ultra-low voltage (ULV) regime with high variation immunity. An ULP near-/sub-threshold 10 transistors (10T) SRAM bit-cell is proposed to be the storage element for improving write variation in ULV regime and eliminate the data-dependent bit-line leakage. The proposed SRAM-based FIFO memory also features adaptive power control circuit, counter-based pointers, and a smart replica read/write control unit. The proposed FIFO is implemented to achieve a minimum operating voltage of 400mV in UMC 90nm CMOS technology. The write power is 2.09W at 50kHz and the read power is 2.25W at 625kHz.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2011
Pages	19-23
Number of pages	5
DOIs	https://doi.org/10.1109/SOCC.2011.6085069
State	Published - 28 Dec 2011
Event	24th IEEE International System on Chip Conference, SOCC 2011 - Taipei, Taiwan Duration: 26 Sep 2011 → 28 Sep 2011

Publication series

Name	International System on Chip Conference
ISSN (Print)	2164-1676
ISSN (Electronic)	2164-1706

Conference

Conference	24th IEEE International System on Chip Conference, SOCC 2011
Country	Taiwan
City	Taipei
Period	26/09/11 → 28/09/11

Access to Document

10.1109/SOCC.2011.6085069

Link to publication in Scopus

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Cite this

Du, W. H., Chang, M. H., Yang, H. Y., & Hwang, W. (2011). An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions. In Proceedings - IEEE International SOC Conference, SOCC 2011 (pp. 19-23). [6085069] (International System on Chip Conference). https://doi.org/10.1109/SOCC.2011.6085069

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title = "An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions",

abstract = "In this paper, an ultra-low power (ULP) 16Kb SRAM-based first-in first-out (FIFO) memory is proposed for wireless body area networks (WBANs). The proposed FIFO memory is capable of operating in ultra-low voltage (ULV) regime with high variation immunity. An ULP near-/sub-threshold 10 transistors (10T) SRAM bit-cell is proposed to be the storage element for improving write variation in ULV regime and eliminate the data-dependent bit-line leakage. The proposed SRAM-based FIFO memory also features adaptive power control circuit, counter-based pointers, and a smart replica read/write control unit. The proposed FIFO is implemented to achieve a minimum operating voltage of 400mV in UMC 90nm CMOS technology. The write power is 2.09W at 50kHz and the read power is 2.25W at 625kHz.",

author = "Du, {Wei Hung} and Chang, {Ming Hung} and Yang, {Hao Yi} and Wei Hwang",

year = "2011",

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doi = "10.1109/SOCC.2011.6085069",

language = "English",

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booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2011",

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}

Du, WH, Chang, MH, Yang, HY & Hwang, W 2011, An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions. in Proceedings - IEEE International SOC Conference, SOCC 2011., 6085069, International System on Chip Conference, pp. 19-23, 24th IEEE International System on Chip Conference, SOCC 2011, Taipei, Taiwan, 26/09/11. https://doi.org/10.1109/SOCC.2011.6085069

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N2 - In this paper, an ultra-low power (ULP) 16Kb SRAM-based first-in first-out (FIFO) memory is proposed for wireless body area networks (WBANs). The proposed FIFO memory is capable of operating in ultra-low voltage (ULV) regime with high variation immunity. An ULP near-/sub-threshold 10 transistors (10T) SRAM bit-cell is proposed to be the storage element for improving write variation in ULV regime and eliminate the data-dependent bit-line leakage. The proposed SRAM-based FIFO memory also features adaptive power control circuit, counter-based pointers, and a smart replica read/write control unit. The proposed FIFO is implemented to achieve a minimum operating voltage of 400mV in UMC 90nm CMOS technology. The write power is 2.09W at 50kHz and the read power is 2.25W at 625kHz.

AB - In this paper, an ultra-low power (ULP) 16Kb SRAM-based first-in first-out (FIFO) memory is proposed for wireless body area networks (WBANs). The proposed FIFO memory is capable of operating in ultra-low voltage (ULV) regime with high variation immunity. An ULP near-/sub-threshold 10 transistors (10T) SRAM bit-cell is proposed to be the storage element for improving write variation in ULV regime and eliminate the data-dependent bit-line leakage. The proposed SRAM-based FIFO memory also features adaptive power control circuit, counter-based pointers, and a smart replica read/write control unit. The proposed FIFO is implemented to achieve a minimum operating voltage of 400mV in UMC 90nm CMOS technology. The write power is 2.09W at 50kHz and the read power is 2.25W at 625kHz.

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