An energy-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms

Kuan Hung Chen*, Jiun-In Guo, Jinn Shyan Wang, Ching Wei Yeh, Jia Wei Chen

*Corresponding author for this work

Research output: Contribution to journalArticle

11 Scopus citations

Abstract

This paper proposes a flexible hardware solution and the associated energy-aware IP core design for computing the variable-length discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) required in the MPEG4 shape-adaptive DCT/IDCT (SA-DCT/IDCT). The proposed IP core has been developed based on the design concept of programmable processors to provide the flexibility in dynamically configuring the hardware. To achieve good performance both in area and speed, we optimize the proposed IP core both in the algorithmic computational complexity and hardware complexity. Furthermore, the proposed IP core possesses the feature of energy-aware design flexibility. The simulation shows that the proposed design has 44% energy reduction at the price of 0.3-dB signal quality degradation for the image compression applications. The implementation results show that the proposed IP core costs about 3100 gates along with 16 words (1 word = 16 bits) of memory, which can achieve the real-time processing of the texture coding in MPEG4 SP@L3 and ACE@L2 CODEC system for the CIF format video at 30 frames/s with 4:2:0 color format.

Original languageEnglish
Pages (from-to)704-715
Number of pages12
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume15
Issue number5
DOIs
StatePublished - 1 May 2005

Keywords

  • Common subexpression sharing
  • Distributed arithmetic
  • MPEG4 object-based video coding
  • SIP design
  • Shape-adaptive discrete cosine transform
  • System-on-a-chip (SoC) design

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