This paper proposes an embedded DSP core for communication applications with targets of demodulation/synchronization operation. Besides providing a basic instruction set, similar to current day 16-bit DSP processors, it contains distinguish instructions, and special function blocks like dual MAC, sub-word multiplier, dedicated FIR filter and multi-levels slicer, which make this DSP processor more efficient for several communication tasks. Also, the entire architecture is parameterized that can be embedded variety applications. In the design of chip, we adapt gray coded addressing for lowing switching activity, pipeline register sharing for reducing pipeline register and the entire architecture is used to reduce power dissipation. The DSP chip is implemented by synthesizable Verilog code with TSMC 0.35 um SPQM cell library. The equivalent gate count of the core without memory is about 50k. The chip area is 4.10mm*4.10mm (with on chip memory).
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 2002|