An efficient VLSI implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters

Bing-Fei Wu*, Yi Qiang Hu

*Corresponding author for this work

Research output: Contribution to journalLetterpeer-review

15 Scopus citations

Abstract

This work presents a VLSI design rule, namely, an embedded instruction code (EIC), for the discrete wavelet transform (DWT). Our approach derives from the essential computations of DWT, and we establish a set of multiplication instructions, MUL, and the addition instruction, ADD. In addition, we propose a parallel arithmetic logic unit (PALU) with two multipliers and four adders, called 2M4A. With these requirements, the DWT computation paths can be calculated more efficiently with limited PALUs. Furthermore, since the EIC is operated under the PALU, the number of needed inner registers depends on the wavelet filters' length. Besides, the boundary problem of DWT has also been resolved by the symmetric extension. Moreover, the two-dimensional inverse DWT (2-D IDWT) can be completed using the same PALU for 2-D DWT; the only changes needed to be made are the instruction codes and coefficients. Our chip supports up to six levels of decomposition and versatile image specifications, e.g., VGA, MPEG-1, MPEG-2 and 1024 × 1024 image sizes.

Original languageEnglish
Article number1233005
Pages (from-to)936-943
Number of pages8
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume13
Issue number9
DOIs
StatePublished - 1 Sep 2003

Keywords

  • Two-dimensional discrete wavelet transform
  • VLSI

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