An Efficient VLSI Architecture for Full-Search Block Matching Algorithms

Chen-Yi Lee*, Mei Cheng Lu

*Corresponding author for this work

Research output: Contribution to journalArticle

8 Scopus citations

Abstract

This paper presents a novel memory-based VLSI architecture for full search block matching algorithms. We propose a semi-systolic array to meet the requirements of high computational complexity, where data communications are handled in two styles: (1) global connections for search data and (2) local connections for partial sum. Data flow is handled by a multiple-port memory bank so that all processor elements function on target data items. Thus hardware efficiency achieved can be up to 100%. Both semi-systolic array structure and related memory management strategies for full-search block matching algorithms are highlighted and discussed in detail in the paper.

Original languageEnglish
Pages (from-to)275-282
Number of pages8
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume15
Issue number3
DOIs
StatePublished - 1 Dec 1997

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