An efficient two-phase ILP-based algorithm for precise CMOS RFIC layout generation

Tsun Ming Tseng, Bing Li, Ching Feng Yeh, Hsiang Chieh Jhan, Zuo-Min Tsai , Po-Hung Lin, Ulf Schlichtmann

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

With advancing process technologies and booming Internet of Things markets, millimeter-wave CMOS RFICs have evolved rapidly and been widely applied in recent years. The performance of CMOS RFICs is very sensitive to the chip layout, and a tiny variation of the microstrip length can cause a large impact to the circuit performance. This results in a time-consuming tuning process including much simulation effort for chip design, which becomes the major bottleneck for time to market. This paper introduces a progressive integer-linearprogramming- based method consisting of two phases: 1) global layout generation and 2) iterative validation. In the global layout generation phase, we focus on the most critical constraints such as layout planarity and device connection relations to determine the topology of the final design. This provides a basis for constructing the accurate model in the iterative validation phase. The layouts generated by applying our method can satisfy very stringent routing requirements of microstrip lines, including spacing/noncrossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both performance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout generation time is significantly reduced from weeks to a few minutes.

Original languageEnglish
Article number7745860
Pages (from-to)1313-1326
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume36
Issue number8
DOIs
StatePublished - 1 Aug 2017

Keywords

  • Circuit optimization
  • Integer linear programming
  • Layout
  • Physical design
  • Radiofrequency integrated circuits

Fingerprint Dive into the research topics of 'An efficient two-phase ILP-based algorithm for precise CMOS RFIC layout generation'. Together they form a unique fingerprint.

Cite this