A new general timing model for CMOS combinational logic gates is proposed. In this model, the linearized large-signal equivalent circuit of a gate is first constructed. Then applying the dominant-pole-dominant-zero (DPDZ) method, the dominant pole of the equivalent circuit is calculated. Using this pole, the signal timing can be explicitly expressed. Comparisons between calculation results and simulation results are made and error analyses are performed. The worst-case error in characteristic-waveform timing can be confined to be within 35 percent for CMOS inverters, multi-input NOR gates or multi-input NAND gates with different device dimensions, capacitive loads, and device parameters. Better accuracy can be obtained for logic gates with commonly-used channel dimension or large capacitive load. For internal waveforms not deviating much from the characteristic waveforms, the worst-case error in signal timing is not substantially increased. Applying the proposed timing model in an experimental timing simulator, the signal timing can be analyzed accurately and efficiently with reduced CPU time and memory.
|Number of pages||15|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - 1 Jan 1985|