An efficient systolic architecture for the DLMS adaptive filter and its applications

Lan-Da Van*, Wu Shiung Feng

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

54 Scopus citations

Abstract

In this paper, we propose an efficient systolic architecture for the delay least-mean-square (DLMS) adaptive finite impulse response (FIR) digital filter based on a new tree-systolic processing element (PE) and an optimized tree-level rule. Applying our tree-systolic P E, a higher convergence rate than that of the conventional DLMS structures can be obtained without sacrificing the properties of the systolic-array architecture. The efficient systolic adaptive FIR digital filter not only operates at the highest throughput in the word-level but also considers finite driving/update of the feedback error signal. Furthermore, based on our proposed optimized tree-level rule that takes account of minimum delay and high regularity, an efficient N-tap systolic adaptive FIR digital filter can be easily determined under the constraint of maximum driving of the feedback error signal.

Original languageEnglish
Pages (from-to)359-366
Number of pages8
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume48
Issue number4
DOIs
StatePublished - 1 Apr 2001

Keywords

  • Adaptive filter
  • DLMS algorithm
  • Equalization
  • System identification
  • Systolic architecture

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