An efficient pipeline architecture and memory bit-width analysis for discrete wavelet transform of the 9/7 filter for JPEG 2000

Chung Fu Lin*, Pei Kung Huang, Bing-Fei Wu

*Corresponding author for this work

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

In this paper, we propose an efficient pipeline architecture for the DWT 9/7 filter defined in JPEG 2000. The proposed architecture is composed of column and row processors to perform the separable 2-D DWT. Based on the rescheduling DWT algorithm, we derive a new data flow graph to shorten the critical path. The proposed 1-D column processor requires less pipeline registers to achieve about the same critical path compared with other lifting-based architectures. For the row processor, the data dependency of each lifting step is reduced to only two computation nodes and therefore more pipeline registers can be applied to achieve higher processing speed without increasing the internal memory size in the 2-D case. That is, for an N×N image, it only requires 4N internal memory to perform the row-wise transform. For the memory bit-width analysis, we use software simulation to reduce the memory bit-width for various compression ratios. Since a portion of information from least significant bits of DWT coefficients would be discarded after EBCOT-tier2 processing, one can decrease the data width of internal memory to perform various compression ratios of JPEG 2000 coding, especially at the low-bit rates. Our simulation results suggest that it is practically possible to design the energy-aware memory architecture to further reduce the power consumption in the future work.

Original languageEnglish
Pages (from-to)245-253
Number of pages9
JournalJournal of Signal Processing Systems
Volume59
Issue number3
DOIs
StatePublished - 1 Jun 2010

Keywords

  • Critical path
  • DWT
  • Energy-aware architecture
  • JPEG 2000
  • Memory bit-width

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