An efficient MOS VLSI timing simulator on parallel computers

Steve S. Chung, Tian-Sheuan Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new timing simulator for MOS VLSI circuits has been developed. It is capable of performing accurate transient analysis, simulating large circuits, and improving the simulation speed. For simulating tightly coupled circuits, floating capacitors are used, and accuracy can be preserved. an efficient subcircuit model with latency exploitation is employed to reduce the simulation time. Benchmark tests on multiprocessors show that the simulation speed is about an order of speed faster than that of single CPUs for a number of circuits.

Original languageEnglish
Title of host publicationProceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
PublisherIEEE Computer Society
Pages495-498
Number of pages4
ISBN (Electronic)0780307682
DOIs
StatePublished - 1 Jan 1992
Event5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 - Rochester, United States
Duration: 21 Sep 199225 Sep 1992

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Conference

Conference5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
CountryUnited States
CityRochester
Period21/09/9225/09/92

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  • Cite this

    Chung, S. S., & Chang, T-S. (1992). An efficient MOS VLSI timing simulator on parallel computers. In Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 (pp. 495-498). [270214] (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASIC.1992.270214