In this paper, the efficient modeling codec architecture for binary shape coding is presented. This novel design includes a memory unit that employs the Address Generation module and the Select & Barrel Shift module to speed up the process of border pixels generation. A simple architecture of the modified modeling unit, which uses a Column-scan map to reduce the number of mux and barrel shifter is proposed. Based on the proposed architecture, it deals with not only context computation of the intra mode but also it of the inter mode on the same hardware architecture. In addition, this design technique is suitable for the context-based arithmetic encode/decode in the whole MPEG-4 codec system.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 2002|
|Event||2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States|
Duration: 26 May 2002 → 29 May 2002