Special hardware such as FPGA can provide higher simulation speed for verification. However, it is very hard to debug due to the poor visibility of internal nodes. In , a snapshot method was proposed to "record" the internal behaviors of an FPGA and "replay" a certain period of time in a software simulator. In the snapshot approach, we can still keep a high simulation speed with a better debugging environment. Although saving the values of all internal registers is a sufficient solution to reconstruct the simulation waveform, it is not the optimal solution for large designs. In this paper, we propose a method to reduce the number of recorded registers in the snapshot approach. Our experiments have shown that both hardware overhead and storage data can be greatly reduced by our approach, which enables the snapshot method to be applied on larger designs.