This paper presents a novel approach for implementing power-efficient finite impulse response (FIT) filters that requires less-power consumption than traditional FIR filter implementation in wireless embedded systems. The proposed schemes impose to the direct form and achieve certain reduction in the power consumption. A novel re-timed structure and balanced modularized techniques are introduced and used to reduce the critical path to achieve hardware efficiency. A novel separated signed processing data flow scheme with modifying CSD (Canonical Signed Digit) representation is also introduced and used to reduce the transition, which is the main source of power consumption. By using a combination of proposed methods, balanced modularized with re-timed techniques and separated processing data flow scheme with modifying CSD representation, the proposed structures are shown with up to 71% reduction in power consumption with slight area overhead.
|Number of pages||8|
|Journal||IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation|
|State||Published - 1 Jan 2001|