An efficient IDCT processor design for HDTV applications

Jiun-In  Guo*, Jui Cheng Yen

*Corresponding author for this work

Research output: Contribution to journalArticle

6 Scopus citations

Abstract

This paper proposes a high performance and low cost inverse discrete cosine transform (IDCT) processor for high definition Television (HDTV) applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate the one-dimensional (I-D) IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multiplier that implements multiplication with IDCT coefficients are first scaled and optimized by using the common sub-expression techniques. Based on these techniques, the data-path in the proposed two-dimensional (2-D) IDCT design costs 7504 gates plus 1024 bits of memory with 100 M pixels/sec throughput according to the cost estimation based on the cell library of COMPASS 0.6μm SPDM CMOS technology. Also, we have verified that the precision analysis of the proposed 2-D 8 × 8 IDCT meets the demands of IEEE Std. 1180-1990. Due to the good performance in the computing speed as well as the hardware cost, the proposed design is compact and suitable for HDTV applications. This design methodology can be applied to forward DCT as well as other transforms like discrete sine transform (DST), discrete Fourier transform (DFT), and discrete Hartley transform (DHT).

Original languageEnglish
Pages (from-to)147-155
Number of pages9
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume33
Issue number1-2
DOIs
StatePublished - 1 Jan 2003

Keywords

  • Adder-based implementation
  • Common sub-expression sharing, HDTV
  • Cyclic convolution
  • Inverse discrete cosine transform (IDCT)

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