An Efficient Hierarchical Banking Structure for Algorithmic Multiported Memory on FPGA

Bo-Cheng Lai*, Kun Hua Huang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

Algorithmic multiported memory supports concurrent accesses by cooperating block RAMs (BRAMs) with algorithmic operations, and demonstrates the better performance per resource usage on FPGA when compared with register-based designs. However, the current approaches still use significant amount of FPGA resources and pose great design challenges when increasing the access ports. This paper proposes HB-NTX with a resource efficient hierarchical banking structure for nontable-based multi-ported memory design on FPGA. The regular design style enables a systematic flow to scale both read and write ports. When compared with the previous approaches, HB-NTX can reduce 62.03% BRAMs when composing a 2R4W memory with 32K depth. This paper further extends the HB-NTX to alleviate the complexity of the table-based memory designs. When compared with the previous table-based TBLVT approach, the proposed design for a 2R4W memory with 8K depth attains the cost reduction of 39.9%, 14.3%, and 15.6%, for registers, lookup tables, and BRAMs, respectively.

Original languageEnglish
Article number7962249
Pages (from-to)2776-2788
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number10
DOIs
StatePublished - 1 Oct 2017

Keywords

  • Algorithmic multiported memory
  • block RAM (BRAM)
  • field-programmable gate array (FPGA)

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